1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor.
2. Description of Related Art
A flat panel display device includes a thin film transistor (TFT). The thin film transistor employs a lightly doped drain (LDD) structure or an off-set structure in order to prevent a leakage current that occurs in an off state thereof. Recently, research to achieve excellent operability of the thin film transistor, for example, by improving electrical characteristics such as a threshold voltage of a channel layer and electron mobility, has been conducted.
FIGS. 1A and 1B are cross-sectional views illustrating a process of manufacturing a conventional CMOS thin film transistor.
Referring to FIG. 1A, a substrate 10 having a first region 10a and a second region 10b is provided. The first region 10a is a region on which a p-type thin film transistor will be formed, and the second region 10b is a region on which an n-type thin film transistor will be formed.
A poly silicon layer is deposited and patterned to form first and second semiconductor layers 11a and 11b on the first and second regions 10a and 10b, respectively. A gate insulating layer 12 is formed over the entire surface of the substrate 10 to cover the first and second semiconductor layers 11a and 11b. 
A metal layer 13 is deposited on the gate insulating layer 12. A first photosensitive layer (not shown) having first and second photoresist patterns is formed on the metal layer 13. The first pattern of the first photosensitive layer is formed over the first semiconductor layer 11a, and the second pattern of the first photosensitive layer covers the entire surface of the second region 10b of the substrate 10. The metal layer 13 is patterned according to the first photosensitive layer, so that a first gate electrode 14a is formed over the first semiconductor layer 11a, and the rest of the metal layer 13 covers the entire surface of the second region 10b. The photoresist pattern is then removed.
A p+-type high-density impurity is ion-doped by an ion implanter that employs an ion-shower method to thereby form first high-density source and drain regions 16a and 16b. 
However, the ion implanter that employs the ion-shower method has no mass separator which removes non-desired impurities (e.g., hydrogen) except a desired impurity (e.g., a p+-type impurity) from the doped impurity. As a result, the non-desired impurities such as a hydrogen ion can be doped to even the first and second semiconductor layers 11a and 11b. 
Subsequently, a second photosensitive layer (not shown) having first and second patterns is formed on the metal layer 13. The first pattern of the second photosensitive layer covers the entire surface of the first region 10a of the substrate 10, and the second pattern of the second photosensitive layer is formed over the second semiconductor layer 11b. The rest of the metal layer 13 covering the entire surface of the second region 10b is patterned according to the second pattern of the second photosensitive layer to thereby form a second gate electrode 14b. 
Using the second photosensitive layer as a mask, an n−-type low-density impurity is ion-doped into the second semiconductor layer 11b to form low-density source and drain regions 18a and 18b. The second photosensitive layer is then removed.
A third photosensitive layer having first and second patterns is formed. The first pattern of the third photosensitive layer covers the entire surface of the first region 10a of the substrate 10. The second pattern of the third photosensitive layer has a greater width than the second gate electrode 14b and so surrounds the second gate electrode 14b. Using the third photoresist layer as a mask, an n+-type high-density impurity is ion-doped into the second semiconductor layer 11b to form second high-density source and drain regions 20a and 20b. Consequently, the CMOS thin film transistor having a lightly doped drain (LDD) structure is completed.
However, as described above, the ion implanter that employs the ion-shower method has no mass separator, which removes non-desired impurities except a desired impurity from the doped impurity. Hence, during an ion doping process to form the first high-density source and drain regions 16a and 16b of the PMOS thin film transistor, the non-desired impurities such as hydrogen ions are ion-doped to even channel regions of the first and second semiconductor layers 11a and 11b under the first and second gate electrodes 14a and 14b. 
In other words, even though the first gate electrode 14a and the non-patterned metal layer 13 block the p+-type impurity from being ion-doped during an ion doping process to form the first high-density source and drain regions 16a and 16b, the hydrogen ions having a relatively small mass pass through the first gate electrode 14a and the non-patterned metal layer 13 to be ion-doped to even the channel regions of the first and second semiconductors 14a and 14b. 
For example, in order to ion-dope a boron (B), a B2H6 gas is decomposed into BX+, BXHY+, and HX+. However, since BXHY+ and HX+ including a hydrogen ion is not removed by the ion implanter that employs the ion shower method, BXHY+ and HX+ as well as BX+ are ion-doped into the first and second semiconductor layers 11a and 11b. 
FIG. 2 illustrates a density of a hydrogen ion doped into respective regions of the thin film transistor after an ion-doping process to form the source and drain regions of the PMOS thin film transistor. As can be seen in FIG. 2, the hydrogen ions are doped into even the semiconductor layer.
Even though a small amount of hydrogen ions are ion-doped into the channel region of the semiconductor layer, the doped hydrogen ions affect an interface characteristic between the semiconductor layer and the gate insulating layer, thereby deteriorating electrical characteristics such as a threshold voltage and an electron mobility and a reliability of the resultant thin film transistor.